1. Field of the Invention
The invention relates to reference buffer circuits, and in particular, to an improved reference buffer circuit with high driving capability.
2. Description of the Related Art
In analog circuit applications, particularly for analog to digital converters (ADCS) such as pipeline ADC, Flash ADC, and SAR ADC, a reference buffer circuit with sufficient driving capability is essential for providing accurate reference voltages. As technology advances, the supply voltage designed for circuit is lower than ever, therefore making it more of a challenge to implement a reference buffer circuit with such low supply voltage while not decreasing its driving capability.
FIG. 1 shows a conventional reference buffer circuit 100. The reference buffer circuit 100 comprises a buffering stage 110 and a driving stage 120 supplied by a supply voltage VDD. The buffering stage 110 provides a high tracking voltage VGH and a low tracking voltage VGL respectively based on a high input voltage VinH and a low input voltage VinL, and the driving stage 120 is driven by the high tracking voltage VGH and the low tracking voltage VGL to output a high output voltage VoutH and a low output voltage VoutL. Specifically, the buffering stage 110 comprises a first NMOS transistor M1 with its drain coupled to the supply voltage VDD, and a first PMOS transistor M2 with its drain coupled to the signal ground. A first operational amplifier OP1 has two input ends and one output end. The first input end (+) is for receiving the high input voltage VinH, the second input end (−) is coupled to the source of the first NMOS transistor M1, and the output end is coupled to the gate of the first NMOS transistor M1. The second operational amplifier OP2 has similar deployment as that of the first operational amplifier OP1. The first input end (+) of the second operational amplifier OP2 is for receiving the low input voltage VinL, the second input end (−) is coupled to the source of the first PMOS transistor M2, and the output end is coupled to the gate of the first PMOS transistor M2. A buffering stage resistor RB is coupled between the sources of the first NMOS transistor M1 and the first PMOS transistor M2. By applying the high input voltage VinH to the first operational amplifier OP1, the first operational amplifier OP1 locks the gate voltage of the first NMOS transistor M1 at a high tracking voltage VGH. Likewise, the second operational amplifier OP2 locks the gate voltage of the first PMOS transistor M2 at a low tracking voltage VGL according to the low input voltage VinL. Thereby, the driving stage 120 is driven by the high tracking voltage VGH and low tracking voltage VGL to accurately output the high output voltage VoutH and low output voltage VoutL.
Specifically, the driving stage 120 comprises two MOS transistors and a resistor. A second NMOS transistor M3 has a drain coupled to the supply voltage VDD, a gate for receiving the high tracking voltage VGH, and a source for outputting the high output voltage VoutH. A second PMOS transistor M4 has a drain coupled to the signal ground, a gate receiving the low tracking voltage VGL, and a source for outputting the low output voltage VoutL. A driving stage resistor RD is coupled between the sources of the second NMOS transistor M3 and the second PMOS transistor M4. The driving stage 120 is also referred to as a replica circuit, in which the high output voltage VoutH and low output voltage VoutL are used as reference voltages that are provided with high driving capability.
With design criteria requiring the supply voltage to be reduced, the low output voltage VoutL also drops. The low output voltage VoutL is likely to be lower than the gate-to-source voltage drop of the second PMOS transistor M4, causing the total driving stage 120 to stop functioning, because the second PMOS transistor M4 would be turned off. Hence, an enhanced circuit structure is desirable which overcomes the issue.